AArch64 MP+dmb.sy+addr-ctrl-addr-[fr-rf]-ctrlisb
"DMB.SYdWW Rfe DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre"
Cycle=Rfe DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre DMB.SYdWW
Relax=
Safe=Rfe Fre DMB.SYdWW DpAddrdR DpCtrldR DpCtrlIsbdR [FrLeave,RfBack]
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr Rf
Orig=DMB.SYdWW Rfe DpAddrdR DpCtrldR DpAddrdR FrLeave RfBack DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X4=z; 1:X6=a; 1:X9=b; 1:X12=x;
2:X1=b;
}
P0 | P1 | P2 ;
MOV W0,#1 | LDR W0,[X1] | MOV W0,#1 ;
STR W0,[X1] | EOR W2,W0,W0 | STR W0,[X1] ;
DMB SY | LDR W3,[X4,W2,SXTW] | ;
MOV W2,#1 | CBNZ W3,LC00 | ;
STR W2,[X3] | LC00: | ;
| LDR W5,[X6] | ;
| EOR W7,W5,W5 | ;
| LDR W8,[X9,W7,SXTW] | ;
| LDR W10,[X9] | ;
| CBNZ W10,LC01 | ;
| LC01: | ;
| ISB | ;
| LDR W11,[X12] | ;
Observed
y=1; x=1; b=1; 1:X8=1; 1:X11=1; 1:X10=0; 1:X0=1;
and y=1; x=1; b=1; 1:X8=1; 1:X11=1; 1:X10=0; 1:X0=0;
and y=1; x=1; b=1; 1:X8=1; 1:X11=0; 1:X10=0; 1:X0=0;